Registers (#3)

* Byte Dataclass

* Added some abbreviations and registers of bank0

* New Bank approach

* implemented indirect Addressing of registers..partially

* Added other unique special registers to bank array

* Working Memory with direct and indirect addressing

* Some simplifications and branch removals

* Added working register

* Removed NewByte.java

* Simplified if statements

* Removed unneccesary check in if

.gitignore

@@ -25,4 +25,6 @@ hs_err_pid*
 #IntelliJ Files
 .idea
 out
-*.iml
+*.iml
+
+*.LST