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DarkressX 9e73a08b8f Registers (#3 )

* Byte Dataclass

* Added some abbreviations and registers of bank0

* New Bank approach

* implemented indirect Addressing of registers..partially

* Added other unique special registers to bank array

* Working Memory with direct and indirect addressing

* Some simplifications and branch removals

* Added working register

* Removed NewByte.java

* Simplified if statements

* Removed unneccesary check in if

2023-05-19 22:24:58 +02:00

.gitignore

Registers (#3 )

2023-05-19 22:24:58 +02:00

CommandDecoder.java

Some commenting

2023-05-09 22:04:08 +02:00

HelloWorld.java

Implemented Program Parser

2023-05-09 22:45:37 +02:00

Parser.java

Implemented Program Parser

2023-05-09 22:45:37 +02:00

README.md

Registers (#3 )

2023-05-19 22:24:58 +02:00

Registers.java

Registers (#3 )

2023-05-19 22:24:58 +02:00

README.md

pic16f84-sim

FSR = File select register > is a pointer:

Addressing INDF actually addresses the register whose address is contained in the FSR register

SFR = Special function register

W = Working register

Status = Status register

GPR = General purpose register; Directly or indirectly accessible through FSR

C = Carry > Status register DC = Digit Carry > Status register Z = ZeroFlag > Status register

INTCON = Interrupt Condition(?) register

SRAM in Bank1 is mappend to Bank0