Registers (#3)

* Byte Dataclass

* Added some abbreviations and registers of bank0

* New Bank approach

* implemented indirect Addressing of registers..partially

* Added other unique special registers to bank array

* Working Memory with direct and indirect addressing

* Some simplifications and branch removals

* Added working register

* Removed NewByte.java

* Simplified if statements

* Removed unneccesary check in if

README.md

@@ -1 +1,22 @@
-# pic16f84-sim
+# pic16f84-sim
+
+FSR = File select register > is a pointer:
+
+Addressing INDF actually addresses the register whose
+address is contained in the FSR register
+
+SFR = Special function register
+
+W = Working register
+
+Status = Status register
+
+GPR = General purpose register; Directly or indirectly accessible through FSR
+
+C = Carry > Status register
+DC = Digit Carry > Status register
+Z = ZeroFlag > Status register
+
+INTCON = Interrupt Condition(?) register
+
+SRAM in Bank1 is mappend to Bank0