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clrfInstruction
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Author SHA1 Message Date
darkress
9a21d9256f implemented Clrf Instruction 2023-06-02 23:50:34 +02:00
darkress
ab9f378d34 implemented Clrw instruction (#15) 
Co-authored-by: darkress <github@darkress.xyz>
Reviewed-on: darkress/pic16f84-sim#15
 2023-06-02 23:29:15 +02:00
darkress
b23bf4c54b implemented Incfsz Instruction (#14) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#14
 2023-05-31 22:30:29 +02:00
darkress
7eab465fff implement Incf Instruction (#13) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#13
 2023-05-31 22:13:12 +02:00
darkress
c896b4f199 decfszInstruction (#12) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#12
 2023-05-31 20:51:00 +02:00
darkress
46515de5f1 implemented Nop Instruction (#11) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#11
 2023-05-31 20:24:57 +02:00
darkress
49ab5876b8 implemented decf Instruction (#10) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#10
 2023-05-31 20:16:46 +02:00
darkress
1f8e3aff58 implemented comf Instruction (#9) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#9
 2023-05-31 20:00:52 +02:00
darkress
c7d062cffd implemented Andwf instruction (#8) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#8
 2023-05-31 19:44:54 +02:00
darkress
7af1145ad4 implemented Addwf Instruction (#7) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#7
 2023-05-31 19:34:56 +02:00
darkress
0b5d0c172a fixed PC (#6) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#6
 2023-05-31 14:22:45 +02:00
darkress
2cfc14ba78 implemented Retlw instruction (#5) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#5
 2023-05-31 02:00:25 +02:00
darkress
eed0b2e3eb implemented return instruction; Fixed Bug in Stack.pop() (#4) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#4
 2023-05-31 01:30:20 +02:00
darkress
666cc2881b callInstruction (#3) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#3
 2023-05-30 01:19:58 +02:00
darkress
1b3529c403 implemented Goto Instruction; Increment ProgramCounter; (#2) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#2
 2023-05-29 18:07:48 +02:00
darkress
bfbec8d525 XorlwInstruction (#1) 
Co-authored-by: Darkress <30271678+DarkressX@users.noreply.github.com>
Reviewed-on: darkress/pic16f84-sim#1
 2023-05-29 15:39:04 +02:00
DarkressX
769c37e5f3 implemented PC (#11) 2023-05-29 00:25:37 +02:00
DarkressX
29ec2afe04 implemented Stack (#10) 2023-05-28 19:30:07 +02:00
DarkressX
5c4aee2da6 Simulating Full SRAM of µC (#9) 2023-05-24 20:51:43 +02:00
DarkressX
5e08c6d728 Functional Sublw instruction (#8) 
* Functional Sublw instruction

* Fixed zeroBit in Addlw after overflow and result == 0
 2023-05-23 17:47:25 +02:00
DarkressX
d5eaee2bde Add Movlw instruction (#7) 2023-05-23 15:19:51 +02:00
DarkressX
347e67c3c8 Added Iorlw Instrction (#6) 2023-05-23 15:12:30 +02:00
DarkressX
8011c0ce40 Andlw instruction (#5) 2023-05-23 15:00:54 +02:00
DarkressX
47cf49abea Addlw instruction (#4) 
* Added addlw command

* Write to program list

* Included CommandUtils as helpter class. Sorted classes into packages

* Revert changes on HelloWorld

* Revert "Revert changes on HelloWorld"

This reverts commit a08a336864fb2aa2bbc5a4e37ca360765774965e.

* Added example execution of Addlw command
 2023-05-22 23:55:01 +02:00
DarkressX
9e73a08b8f Registers (#3) 
* Byte Dataclass

* Added some abbreviations and registers of bank0

* New Bank approach

* implemented indirect Addressing of registers..partially

* Added other unique special registers to bank array

* Working Memory with direct and indirect addressing

* Some simplifications and branch removals

* Added working register

* Removed NewByte.java

* Simplified if statements

* Removed unneccesary check in if
 2023-05-19 22:24:58 +02:00
Darkress
97a75622f9 Implemented Program Parser 2023-05-09 22:45:37 +02:00
Darkress
3cda4057ac Some commenting 2023-05-09 22:04:08 +02:00
Darkress
f575fc81c9 'Simplified' decoder by using switches 2023-05-09 22:04:08 +02:00
darkress
aea57b5eec Implemented basic command detector 2023-05-09 22:04:08 +02:00
darkress
5acbf36c9b Added CommandDecoder for all Byte-oriented file register operations 2023-04-17 16:18:14 +02:00
darkress
15eecb050b Corrected mistake in CLRF, CLRW 2023-04-17 15:27:48 +02:00
darkress
5a0dbf47d1 Added CommandDecoder for CLRF, CRLW, COMF, DECF 2023-04-17 15:12:52 +02:00
darkress
5468cce530 Init 2023-04-17 14:52:12 +02:00
DarkressX
092d85a7b0 Initial commit 2023-04-17 13:40:48 +02:00